The present invention relates generally to semiconductor integrated circuits, and more particularly to design of semiconductor integrated circuits using standard cell methodologies.
Semiconductor integrated circuits are often very complex. The circuits may include thousands or even millions of gates, in various groups performing a variety of functions. The gates often are designed to operate in a timed manner, with operation of the gates synchronized by one or more clock signals, with the speed of operation of the gates often dependent on manufacturing process variations, power supply voltage variations, and temperature variations.
Automated tools are often used in the design of the semiconductor integrated circuits in view of their complexity. The automated tools may provide various functions, but such tools often provide a designer the capability to specify circuit function at a relatively high level, with the tools decomposing the high level description to a low level implementation, determining placement of low level implementation components within a chip, and determining routing of signals within the chip.
Very often the automated tools use standardized components from a library of standardized components in decomposing the high level description to a low level implementation. Each standardized component may include several possible variations, for example variations of numbers of driving transistors, buffers, transistor length/width ratios, or other matters. The different standardized components may be used by the tools to increase speed of certain gates or to increase hold times to reach timing goals or for a variety of other reasons.
Proper timing operation of semiconductor integrated circuits is often very important, desired functions of the circuits may not be properly performed if timing goals of components of the circuitry and the circuitry as a whole are not met. Unfortunately, integrated circuits characteristics may vary chip to chip, although more commonly lot to lot, based on implantation variability, material impurities, or other factors, and in operation may vary based on operating voltage or temperature variations.
Automated tools, therefore, often check expected circuit timing against different locations on the expected curves of process, voltage and temperature variations. In many instances timing is checked against a “slow” position on the curves and a “fast” position on the curves, although some tools may check timing against a variety of points on the curves, or against multiple curves for each variable.
Generally the automated tools account for the timing variations by using different components from the library, or by inserting additional library elements to perform more operations in parallel. The tools may also place additional library components in a chain of elements to increase hold time. Often the changes result in higher power components, or additional power requiring components, and often the requirement for additional power is driven by a need to increase speed of switching or signal rise times. Increased number of components or size of components, however, often results in increased chip size requirements and power requirements, which are often undesirable.